CPC H01L 27/14603 (2013.01) [H01L 27/14612 (2013.01); H01L 27/14658 (2013.01); H01L 27/14692 (2013.01)] | 15 Claims |
1. A flat panel detector substrate, comprising:
a base substrate;
a photoelectric conversion layer located on the base substrate, the photoelectric conversion layer having a first surface proximate to the base substrate and a second surface away from the base substrate;
a bias signal line located between the photoelectric conversion layer and the base substrate; and
a conductive structure located on the base substrate, one end of the conductive structure being coupled to the second surface of the photoelectric conversion layer, another end of the conductive structure being coupled to the bias signal line, and a portion therebetween being located beside the photoelectric conversion layer;
the flat panel detector substrate further comprising:
a thin film transistor located between the photoelectric conversion layer and the base substrate, the thin film transistor including a gate, an active layer, a source and a drain, the source being coupled to the first surface of the photoelectric conversion layer, and an orthographic projection of the active layer of the thin film transistor on the base substrate being located within an orthographic projection of the photoelectric conversion layer on the base substrate;
a gate line provided in a same layer as the gate of the thin film transistor, the gate being coupled to the gate line, and a film layer in which the gate and the gate line are located being a gate layer; and
a data line provided in a same layer as the source and drain of the thin film transistor, the source being coupled to the data line, a film layer in which the source, the drain, and the data line are located being a source-drain layer, and the source-drain layer being located on a side of the gate layer away from the base substrate;
wherein the bias signal line is located in the gate layer; and
the flat panel detector substrate further comprises:
a first insulating layer located between the gate layer and the source-drain layer, the first insulating layer including a first via; and
a first transfer electrode located in the source-drain layer, the first transfer electrode being coupled to the bias signal line through the first via, and the first transfer electrode being further coupled to the second surface of the photoelectric conversion layer; wherein the first transfer electrode forms the other end of the conductive structure.
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