| CPC H01L 25/0652 (2013.01) [G11C 5/06 (2013.01); H01L 21/50 (2013.01); H01L 23/4951 (2013.01); H01L 24/14 (2013.01); H01L 24/95 (2013.01); H10B 20/50 (2023.02); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H01L 2021/60007 (2013.01)] | 14 Claims |
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1. A memory device comprising:
a substrate;
a controller die attached to the substrate;
a flip chip die attached to the substrate, adjacent to the controller die, and in electrical communication with the controller die by way of the substrate;
a first silicon die having a bottom surface attached to one of the substrate or a top surface of the flip chip die, the first silicon die including a first contact pad surface opposite to the bottom surface;
a second silicon die attached to the first contact pad surface of the first silicon die, the second silicon die including a second contact pad surface;
one or more bond wires that electrically connect the first and second contact pad surfaces to the substrate, thereby electrically connecting the first and second silicon dies to the controller die by way of the substrate,
wherein the flip chip die and the first and second silicon dies comprise memory dies,
wherein the flip chip die is configured as a single-level cell (SLC) memory and the first and second silicon dies are configured as one of a multi-level cell (MLC) memory, a triple-level cell (TLC) memory, and a quad-level cell (QLC) memory,
wherein the controller die is configured to:
control the flip chip die to store hot data, and
control the first and second silicon dies to store cold data,
wherein the cold data is a portion of the hot data moved from the flip chip die to the first silicon die, the second silicon die, or a combination of the first silicon die and the second silicon die, and
wherein the controller die is further configured to:
store only the cold data in the first and second silicon dies, wherein all of the cold data is first written to the flip chip die as the hot data before being moved from the flip chip die to the first silicon die, the second silicon die, or the combination of the first silicon die and the second silicon die.
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