US 12,021,035 B2
Interconnecting dies by stitch routing
Sanjay Dabral, Cupertino, CA (US); and Jun Zhai, Cupertino, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 12, 2022, as Appl. No. 17/931,343.
Application 17/931,343 is a continuation of application No. 17/216,278, filed on Mar. 29, 2021, granted, now 11,476,203, issued on Oct. 18, 2022.
Application 17/216,278 is a continuation of application No. 16/583,082, filed on Sep. 25, 2019, granted, now 10,985,107, issued on Apr. 20, 2021.
Application 16/583,082 is a continuation of application No. 15/801,163, filed on Nov. 1, 2017, granted, now 10,438,896, issued on Oct. 8, 2019.
Claims priority of provisional application 62/484,330, filed on Apr. 11, 2017.
Prior Publication US 2023/0052432 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 23/488 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/58 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5389 (2013.01) [H01L 22/32 (2013.01); H01L 23/488 (2013.01); H01L 23/49838 (2013.01); H01L 23/522 (2013.01); H01L 23/5283 (2013.01); H01L 23/58 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 25/18 (2013.01); H01L 22/34 (2013.01); H01L 24/06 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A die structure comprising:
a semiconductor substrate;
a first front-end-of-the line (FEOL) die area of a first die patterned into the semiconductor substrate, the first FEOL die area including a first input/output circuit region;
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area, wherein the BEOL build-up structure further comprises a first metallic seal adjacent to the first input/output circuit region; and
a die edge adjacent to the first input/output circuit region;
wherein the BEOL build-up structure comprises a die-to-die routing connected between the first input/output circuit region and a terminal end of die-to-die routing at the die edge, and the die-to-die routing extends through first openings in the first metallic seal.