| CPC G11C 16/0483 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 17 Claims |
|
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
an array of NAND memory strings; and
a first semiconductor layer in contact with sources of the array of NAND memory strings;
a second semiconductor structure comprising:
a first peripheral circuit of the array of NAND memory strings, the first peripheral circuit comprising a first transistor; and
a second semiconductor layer in contact with the first transistor;
a third semiconductor structure comprising:
a second peripheral circuit of the array of NAND memory strings, the second peripheral circuit comprising a second transistor; and
a third semiconductor layer in contact with the second transistor;
a first bonding interface between the first semiconductor structure and the second semiconductor structure, wherein the second semiconductor layer is between the first bonding interface and the first peripheral circuit; and
a second bonding interface between the second semiconductor structure and the third semiconductor structure, wherein the third semiconductor layer is between the second bonding interface and the second peripheral circuit.
|