CPC G09G 3/3607 (2013.01) [G09G 2300/0852 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0242 (2013.01); G09G 2320/028 (2013.01); G09G 2320/0626 (2013.01)] | 17 Claims |
1. A pixel circuit, comprising:
a plurality of pixel driving modules, wherein each of the pixel driving modules comprises:
a primary pixel control assembly comprising a primary switch and a primary pixel electrode, wherein the primary switch is configured to be controlled by a scan signal on a present-stage scan line to transfer a data signal on a data line to the primary pixel electrode;
a secondary pixel control assembly comprising a secondary switch and a secondary pixel electrode, wherein the secondary switch is configured to be controlled by the scan signal on the present-stage scan line to transmit the data signal on the data line to the secondary pixel electrode;
a sharing switch configured to be controlled by a sharing scan signal on a sharing scan line to reduce the electric potential at the secondary pixel electrode, wherein a control terminal of the sharing switch is controllable independently of a control terminal of the primary switch and a control terminal of the secondary switch, lengths of time that the electric potential at the secondary pixel electrode is at a high electric potential and at a low electric potential are adjustable by the sharing scan signal, the sharing scan signal is configured to control a length of time of turning on and turning off of the sharing switch; and
wherein the present-stage scan line and the sharing scan line are insulated from each other; and the scan signal on the scan line is configured to have a first positive-level pulse, and the sharing scan signal on the sharing scan line is configured to have a second positive-level pulse, the second positive-level pulse is later than the first positive-level pulse, and there is an interval of time between the first positive-level pulse and the second positive-level pulse.
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