| CPC G09G 3/32 (2013.01) [G09G 2300/0426 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01)] | 20 Claims |
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1. A display panel, comprising:
a pixel circuit;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein:
a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1;
when the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2, F1>F2>0;
the pixel circuit includes a driving transistor, a first transistor, and a second transistor;
the driving circuit includes:
a first driving circuit configured to provide a control signal to the first transistor; and
a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes:
a first clock signal line configured to provide a first clock signal to the first driving circuit; and
a second clock signal line configured to provide a second clock signal to the second driving circuit;
when the pixel circuit is operated in the holding stage, a time length when a clock pulse frequency of the first clock signal is the second frequency F2 is H1, a time length when a clock pulse frequency of the second clock signal is the second frequency F2 is H2, and H1>H2≥0.
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