| CPC G06F 7/5443 (2013.01) [G06F 7/50 (2013.01)] | 18 Claims |
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1. A neural network accelerator, comprising:
an instruction decoder configured to decode a neural network computation instruction from a processor into a weight load control signal, an activation load control signal, and a compute control signal;
a plurality of weight selectors configured to obtain weights according to the weight load control signal, wherein the weight load control signal indicates whether to obtain the weights from a weight cache or from a weight generator;
a plurality of activation selectors configured to obtain activations or vectors from a memory according to the activation load control signal, wherein the activation load control signal indicates whether to obtain the activations or the vectors; and
a plurality of lanes of circuits, each lane of circuits being configured to:
receive the weights obtained by the plurality of weight selectors and the activations or the vectors obtained by the plurality of activation selectors,
determine whether to perform convolution operations or vector operations according to the compute control signal, and
perform the convolution operations or vector operations based on the weights and the activations or the vectors to generate output data; and
wherein the instruction decoder is further configured to, in response to the weights have a pattern, instruct the plurality of weight selectors to obtain the weights from the weight generator rather than obtaining the weights from the weight cache to reduce memory access.
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