US 12,019,915 B2
Hardware based status collector acceleration engine for memory sub-system operations
Fangfang Zhu, San Jose, CA (US); Jiangli Zhu, San Jose, CA (US); Ying Tai, Mountain View, CA (US); and Wei Wang, Dublin, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 24, 2022, as Appl. No. 17/703,902.
Application 17/703,902 is a continuation of application No. 16/916,934, filed on Jun. 30, 2020, granted, now 11,288,013.
Claims priority of provisional application 62/874,456, filed on Jul. 15, 2019.
Prior Publication US 2022/0283744 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); G06F 11/1076 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by hardware of a memory sub-system, a first command associated with a set of management units to perform an operation;
writing a pattern to each management unit of the set of management units based at least in part on receiving the first command, wherein the pattern corresponds to an arrangement of logic states for the set of management units;
dividing, by the hardware of the memory sub-system and based at least in part on writing the pattern, the first command into a set of second commands, each second command associated with a respective management unit of the set of management units; and
performing, by the hardware of the memory sub-system, the operation on each management unit of the set of management units based at least in part on dividing the first command into the set of second commands.