US 12,019,269 B2
Multi-chip packaging of silicon photonics
Roy Edward Meade, Lafayette, CA (US); Chong Zhang, San Jose, CA (US); Haiwei Lu, San Jose, CA (US); and Chen Li, San Jose, CA (US)
Assigned to Ayar Labs, Inc., Santa Clara, CA (US)
Filed by Ayar Labs, Inc., Santa Clara, CA (US)
Filed on Nov. 15, 2022, as Appl. No. 17/987,485.
Application 17/987,485 is a continuation of application No. 17/070,601, filed on Oct. 14, 2020, granted, now 11,500,153, issued on Nov. 15, 2022.
Claims priority of provisional application 62/915,632, filed on Oct. 15, 2019.
Prior Publication US 2023/0070458 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G02B 6/122 (2006.01); G02B 6/12 (2006.01)
CPC G02B 6/1225 (2013.01) [G02B 6/12011 (2013.01); G02B 2006/1213 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A package assembly, comprising:
a substrate; and
a semiconductor chip attached to the substrate such that a portion of the semiconductor chip overhangs an edge of the substrate, wherein a v-groove array for receiving a plurality of optical fibers is present within the portion of the semiconductor chip that overhangs the edge of the substrate, wherein the semiconductor chip includes a dam structure formed on the portion of the semiconductor chip that overhangs the edge of the substrate at a location between the v-groove array and the substrate, wherein the dam structure protrudes out from a surface of the semiconductor chip in which the v-groove array is formed, wherein the dam structure extends substantially parallel to the edge of the substrate, wherein the dam structure is spaced apart from the substrate so that a gap exists between the dam structure and the edge of the substrate.