US 12,342,727 B2
Magnetoresistive random-access memory (MRAM) structure for improving process control and method of fabricating thereof
Hsiang-Lun Kao, Taoyuan County (TW); Chen-Chiu Huang, Taichung (TW); Chien-Hua Huang, Miaoli County (TW); and Chung-Te Lin, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jan. 31, 2022, as Appl. No. 17/589,018.
Claims priority of provisional application 63/275,542, filed on Nov. 4, 2021.
Prior Publication US 2023/0138005 A1, May 4, 2023
Int. Cl. H10N 50/01 (2023.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC H10N 50/01 (2023.02) [H10B 61/22 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a multilayer interlevel dielectric (ILD) layer having a metal-and-oxygen containing dielectric layer disposed between a first dielectric layer and a second dielectric layer;
forming a bottom electrode via in the multilayer ILD layer, wherein the bottom electrode via extends through the first dielectric layer, the metal-and-oxygen containing dielectric layer, and the second dielectric layer to an underlying electrically conductive feature;
forming a bottom electrode layer over the second dielectric layer of the multilayer ILD layer and the bottom electrode via, magnetic tunnel junction (MTJ) layers over the bottom electrode layer, and a top electrode layer over the MTJ layers; and
etching the bottom electrode layer, the MTJ layers, and the top electrode layer to form a bottom electrode, an MTJ element, and a top electrode, respectively, of a memory, wherein the etching forms a recess in the multilayer ILD layer that extends to the metal-and-oxygen containing dielectric layer of the multilayer ILD layer; and
etching of the metal-and-oxygen containing dielectric layer that causes metal-containing dielectric spacers to form along sidewalls of the bottom electrode of the memory.