US 12,342,617 B2
Microelectronic device with two field-effect transistors
Sylvain Barraud, Grenoble (FR); and Joris Lacord, Grenoble (FR)
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed by COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed on Jun. 22, 2023, as Appl. No. 18/339,319.
Claims priority of application No. 22 06178 (FR), filed on Jun. 22, 2022.
Prior Publication US 2024/0030221 A1, Jan. 25, 2024
Int. Cl. H10D 30/63 (2025.01); H03K 17/687 (2006.01); H10D 86/00 (2025.01)
CPC H10D 86/201 (2025.01) [H03K 17/687 (2013.01); H10D 30/637 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A microelectronic device comprising:
a field-effect n-MOS transistor comprising a first drain, a first source, a first gate and a first gate oxide,
a first N-doped zone, constituting one from among the first drain and the first source,
a second N-doped zone, constituting the other from among the first drain and the first source,
a field-effect p-MOS transistor comprising a second drain, a second source, a second gate and a second gate oxide,
a first P-doped zone, constituting the second source, if the first N-doped zone constitutes the first drain, or the second drain, if the first N-doped zone constitutes the first source,
second P-doped zone, constituting the other from among the second drain and the second source,
a dielectric layer having an upper face in contact with the first N-doped zone, with the second N-doped zone, with the first P-doped zone and with the second P-doped zone, and
a rear gate in contact with a lower face of the dielectric layer,
wherein the second N-doped zone and the second P-doped zone form a PN junction.