US 12,342,615 B2
Semiconductor device and method of manufacturing the same
Shinya Yamakawa, Kanagawa (JP); and Yasushi Tateshita, Kanagawa (JP)
Assigned to Sony Group Corporation, Tokyo (JP)
Filed by Sony Group Corporation, Tokyo (JP)
Filed on Apr. 6, 2023, as Appl. No. 18/296,793.
Application 18/296,793 is a continuation of application No. 17/245,638, filed on Apr. 30, 2021, granted, now 11,664,376.
Application 17/245,638 is a continuation of application No. 16/727,218, filed on Dec. 26, 2019, granted, now 11,011,518, issued on May 18, 2021.
Application 16/727,218 is a continuation of application No. 16/241,395, filed on Jan. 7, 2019, granted, now 10,559,567, issued on Feb. 11, 2020.
Application 16/241,395 is a continuation of application No. 15/852,041, filed on Dec. 22, 2017, granted, now 10,269,801, issued on Apr. 23, 2019.
Application 15/852,041 is a continuation of application No. 15/154,365, filed on May 13, 2016, granted, now 9,881,920, issued on Jan. 30, 2018.
Application 15/154,365 is a continuation of application No. 14/669,803, filed on Mar. 26, 2015, granted, now 9,449,974, issued on Sep. 20, 2016.
Application 14/669,803 is a continuation of application No. 12/530,797, granted, now 9,070,783, issued on Jun. 30, 2015, previously published as PCT/JP2008/053424, filed on Feb. 27, 2008.
Claims priority of application No. 2007-072968 (JP), filed on Mar. 20, 2007; and application No. 2008-018513 (JP), filed on Jan. 30, 2008.
Prior Publication US 2023/0246032 A1, Aug. 3, 2023
Int. Cl. H10D 84/85 (2025.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/856 (2025.01) [H01L 21/28518 (2013.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H10D 30/0212 (2025.01); H10D 30/601 (2025.01); H10D 30/792 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 64/017 (2025.01); H10D 64/62 (2025.01); H10D 84/0165 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0184 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a side wall insulating film formed on a semiconductor substrate with a trench;
a gate insulating film and a gate electrode formed on the semiconductor substrate within the trench;
a first stress applying film formed after the trench is form and located along the side wall insulating film over the semiconductor substrate; and
source/drain regions formed in the semiconductor substrate on opposite sides of the gate electrode.