US 12,342,613 B2
Low leakage device
Cheng-Ting Chung, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); and Kuan-Lun Cheng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 7, 2022, as Appl. No. 17/859,638.
Application 17/859,638 is a division of application No. 16/802,311, filed on Feb. 26, 2020, granted, now 11,404,417.
Prior Publication US 2022/0336461 A1, Oct. 20, 2022
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/853 (2025.01) [H01L 21/0212 (2013.01); H01L 21/30604 (2013.01); H10D 30/6735 (2025.01); H10D 62/021 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 62/292 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 64/517 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, comprising:
forming on a substrate a layer stack comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
forming a first plurality of fin elements from the layer stack in a first area of the substrate;
forming a second plurality of fin elements from the layer stack in a second area of the substrate;
forming a first plurality of dummy gate stacks over channel regions of the first plurality of fin elements;
forming a second plurality of dummy gate stacks over channel regions of the second plurality of fin elements;
depositing a spacer layer over the first plurality of dummy gate stacks, the second plurality of dummy gate stacks, top surface of source/drain regions of the first plurality of fin elements, and source/drain regions of the second plurality of fin elements;
selectively depositing a polymeric layer over the spacer layer disposed over the first plurality of dummy gate stacks while the spacer layer disposed over the second plurality of dummy gate stacks is not covered by the polymeric layer; and
after the selectively depositing, anisotropically etching the spacer layer, the polymeric layer over the first plurality of dummy gate stacks, the source/drain regions of the first plurality of fin elements, and the source/drain regions of the second plurality of fin elements to form a first plurality of source/drain trenches in the first area and a second plurality of source/drain trenches in the second area,
wherein the anisotropic etching forms, from the spacer layer, a first spacer layer over sidewalls of the first plurality of dummy gate stacks and a second spacer layer over sidewalls of the second plurality of dummy gate stacks,
wherein the anisotropic etching etches the polymeric layer and the spacer layer disposed over the second plurality of dummy gate stacks before it starts to etch the spacer layer disposed over the first plurality of dummy gate stacks.