US 12,342,612 B2
Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions
Leonard P. Guler, Hillsboro, OR (US); Biswajeet Guha, Hillsboro, OR (US); Tahir Ghani, Portland, OR (US); and Swaminathan Sivakumar, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 16, 2023, as Appl. No. 18/511,604.
Application 17/846,439 is a division of application No. 16/134,719, filed on Sep. 18, 2018, granted, now 11,398,474, issued on Jul. 26, 2022.
Application 18/511,604 is a continuation of application No. 17/846,439, filed on Jun. 22, 2022, granted, now 11,862,635.
Prior Publication US 2024/0088142 A1, Mar. 14, 2024
Int. Cl. H10D 84/83 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/834 (2025.01) [H10D 30/6211 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 64/512 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 30/6219 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first fin and a second fin above a substrate, the second fin having a horizontal width greater than a horizontal width of the first fin;
a first gate stack over the first fin;
a second gate stack over the second fin;
first epitaxial source or drain structures at ends of the first fin;
second epitaxial source or drain structures at ends of the second fin, wherein the second epitaxial source or drain structures have an uppermost surface above an uppermost surface of the first epitaxial source or drain structures; and
an intervening dielectric structure between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.