| CPC H10D 84/83 (2025.01) [H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/26513 (2013.01); H01L 21/2652 (2013.01); H01L 21/266 (2013.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 62/822 (2025.01); H10D 62/832 (2025.01); H10D 62/8325 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0144 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01); H10D 30/60 (2025.01); H10D 64/68 (2025.01)] | 20 Claims |
|
1. A method of fabricating a semiconductor device, the method comprising:
forming a first gate structure and a second gate structure over a core device region of a substrate;
forming stressors at opposite sides of the first gate structure;
doping the stressors to form a first source region and a first drain region of a first device; and
doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, the first source region comprises a different material from the second source region, and doping the stressors comprises using a same doping process as doping into the substrate.
|
|
5. A method of manufacturing a semiconductor device, the method comprising:
epitaxially growing a strained material in a first recess on a first side of a first gate structure and in a second recess on a second side of the first gate structure, wherein the first gate structure is in a core region of a substrate;
doping the strained material to have a first conductivity type, wherein doping the strained material comprises doping the strained material after completion of epitaxially growing the strained material;
implanting first dopants in the substrate on a first side of a second gate structure and on a second side of the second gate structure, wherein the first dopants have the first conductivity type, and the second gate structure is in the core region of the substrate;
implanting second dopants in the substrate on a first side of a third gate structure and on a second side of the third gate structure, wherein the third gate structure is in an input/output (I/O) region of the substrate; and
raising a threshold voltage of the second gate structure by implanting third dopants into the substrate to define a doped channel region, and a top-most surface of the doped channel region is co-planar with a top-most surface of the substrate.
|
|
12. A method of fabricating a semiconductor device, the method comprising:
forming a first gate structure and a second gate structure over a core device region of a substrate;
forming stressors at opposite sides of the first gate structure, wherein forming the stressors comprise epitaxially growing a strained material in a first recess on a first side of the first gate structure and in a second recess on a second side of the first gate structure;
doping the stressors to form a first source region and a first drain region of a first device;
implanting first dopants into the substrate at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, and the first source region comprises a different material from the second source region;
forming a third gate structure over the substrate, wherein the third gate structure is in an input/output (I/O) region of the substrate;
implanting second dopants in the substrate on a first side of the third gate structure and on a second side of the third gate structure; and
implanting third dopants into the substrate in the core device region to define a doped channel region in the substrate, wherein forming the second gate structure comprises forming the second gate structure overlapping an entirety of the doped channel region.
|