US 12,342,606 B2
Semiconductor device and method of manufacturing semiconductor device
Hiroyuki Nakamura, Fukuoka (JP); and Shinya Soneda, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
Filed on Dec. 6, 2022, as Appl. No. 18/062,475.
Application 18/062,475 is a division of application No. 16/875,457, filed on May 15, 2020, granted, now 11,610,882.
Application 16/875,457 is a division of application No. 15/851,447, filed on Dec. 21, 2017, abandoned.
Claims priority of application No. 2017-085001 (JP), filed on Apr. 24, 2017.
Prior Publication US 2023/0106654 A1, Apr. 6, 2023
Int. Cl. H10D 84/40 (2025.01); H10D 8/01 (2025.01); H10D 12/00 (2025.01); H10D 12/01 (2025.01); H10D 62/10 (2025.01); H10D 84/80 (2025.01); H10D 8/00 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/60 (2025.01); H10D 62/83 (2025.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01)
CPC H10D 84/403 (2025.01) [H10D 8/045 (2025.01); H10D 12/032 (2025.01); H10D 12/441 (2025.01); H10D 62/102 (2025.01); H10D 62/115 (2025.01); H10D 84/811 (2025.01); H10D 8/00 (2025.01); H10D 62/124 (2025.01); H10D 62/133 (2025.01); H10D 62/137 (2025.01); H10D 62/177 (2025.01); H10D 62/393 (2025.01); H10D 62/60 (2025.01); H10D 62/8303 (2025.01); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an insulated gate bipolar transistor (IGBT) arranged therein, and a withstand-voltage retention region surrounding said first region and said second regions in plan view are defined, said semiconductor substrate having a first main surface and a second main surface;
a surface electrode arranged on said first main surface of a region that includes at least said first region and said withstand-voltage retention region; and
a back-surface electrode arranged on said second main surface of a region that includes at least said first region and said withstand-voltage retention region,
said semiconductor substrate further comprising:
an anode layer having a first conductivity type, which is arranged in said first main surface of said first region;
a diffusion layer having said first conductivity type, which is arranged in said first main surface of said withstand-voltage retention region;
a drift layer having a second conductivity type;
a separating region having a second conductivity type, which is interposed between said anode layer and said diffusion layer and is arranged in said first main surface, the separating region having an impurity concentration different from that of the drift layer; and
a cathode layer having the second conductivity type, which is arranged in said second main surface of said first region.