US 12,342,604 B2
Fin isolation structures of semiconductor devices
Kuo-Cheng Chiang, Hsinchu County (TW); Chih-Hao Wang, Hsinchu County (TW); Kuan-Lun Cheng, Hsin-Chu (TW); and Yen-Ming Chen, Hsin-Chu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/875,009.
Application 17/875,009 is a division of application No. 17/001,211, filed on Aug. 24, 2020, granted, now 11,404,324.
Application 16/204,892 is a division of application No. 15/718,752, filed on Sep. 28, 2017, granted, now 10,714,394, issued on Jul. 14, 2020.
Application 17/001,211 is a continuation of application No. 16/204,892, filed on Nov. 29, 2018, granted, now 10,755,983.
Prior Publication US 2022/0367288 A1, Nov. 17, 2022
Int. Cl. H10D 84/00 (2025.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/02236 (2013.01); H01L 21/76202 (2013.01); H10D 30/0243 (2025.01); H10D 84/0151 (2025.01); H10D 84/834 (2025.01); H10D 84/0158 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming, on a substrate, first and second fin portions of a fin structure, wherein the second fin portion is on the first fin portion;
forming a first insulating layer surrounding the first fin portion;
forming a second insulating layer surrounding the second fin portion;
removing a portion of the second insulating layer to expose a region of the second fin portion;
modifying the region of the second fin portion; and
forming a gate structure on an unexposed region of the second fin portion.