US 12,342,599 B2
Manufacturing method of semiconductor device including gate oxide layer
Ming-Hua Tsai, Tainan (TW); Jung Han, New Taipei (TW); Ming-Chi Li, Tainan (TW); Chih-Mou Lin, Tainan (TW); Yu-Hsiang Hung, Tainan (TW); Yu-Hsiang Lin, Kaohsiung (TW); and Tzu-Lang Shih, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jun. 28, 2024, as Appl. No. 18/757,573.
Application 18/078,057 is a division of application No. 17/369,985, filed on Jul. 8, 2021, granted, now 11,626,500, issued on Apr. 11, 2023.
Application 18/757,573 is a continuation of application No. 18/078,057, filed on Dec. 8, 2022, granted, now 12,057,483.
Claims priority of application No. 202110558119.0 (CN), filed on May 21, 2021.
Prior Publication US 2024/0355894 A1, Oct. 24, 2024
Int. Cl. H10D 64/27 (2025.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 64/516 (2025.01) [H10D 30/0227 (2025.01); H10D 30/601 (2025.01); H10D 62/102 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor device, comprising:
forming a first gate oxide layer on a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, the first gate oxide layer is formed on the first region, and the first gate oxide layer comprises:
a main portion; and
an edge portion having a sloping sidewall;
forming a second gate oxide layer on the second region of the semiconductor substrate, wherein a thickness of the first gate oxide layer is greater than a thickness of the second gate oxide layer;
forming a first dummy gate structure on the first gate oxide layer;
forming a second dummy gate structure on the second gate oxide layer;
forming a first spacer structure on a sidewall of the first dummy gate structure, wherein the first spacer structure is formed on the main portion of the first gate oxide layer;
forming a second spacer structure on a sidewall of the second dummy gate structure;
forming a first source/drain doped region in the semiconductor substrate, wherein the first source/drain doped region is disposed adjacent to the edge portion of the first gate oxide layer, and the first source/drain doped region comprises:
a first portion disposed under the edge portion of the first gate oxide layer in a vertical direction; and
a second portion connected with the first portion;
forming a second source/drain doped region in the second region of the semiconductor substrate, wherein the second source/drain doped region is located adjacent to the second spacer structure;
forming a first metal silicide layer, wherein at least a part of the first metal silicide layer is disposed in the second portion of the first source/drain doped region, and the edge portion of the first gate oxide layer is located between the first spacer structure and the first metal silicide layer in a horizontal direction; and
forming a second metal silicide layer, wherein at least a part of the second metal silicide layer is disposed in the second source/drain doped region, and a first distance between the first metal silicide layer and the first dummy gate structure in the horizontal direction is greater than a second distance between the second metal silicide layer and the second dummy gate structure in the horizontal direction.