US 12,342,578 B2
Stacked layer memory suitable for SRAM and having a long cell
Brent A. Anderson, Jericho, VT (US); Albert M. Chu, Nashua, NH (US); Ruilong Xie, Niskayuna, NY (US); Junli Wang, Slingerlands, NY (US); and Carl Radens, LaGrangeville, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 21, 2022, as Appl. No. 17/991,243.
Prior Publication US 2024/0172408 A1, May 23, 2024
Int. Cl. H10D 30/67 (2025.01); H10B 10/00 (2023.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01)
CPC H10D 30/6757 (2025.01) [H10B 10/12 (2023.02); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 30/62 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A stacked layer memory for a static random-access memory, comprising:
a first layer of the static random-access memory, wherein the first layer comprises a plurality of transistors of a first type;
a second layer of the static random-access memory, wherein the second layer comprises a plurality of transistors of a second type, and the first and second layers are different layers stacked vertically; and
wherein a width of individual static random-access memory cells of the stacked layer memory is defined at least by a pitch of a single transistor of the plurality of transistors of the first type and the plurality of transistors of the second type.