US 12,342,572 B2
Semiconductor device
Tatsuya Shiraishi, Nonoichi Ishikawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Sep. 6, 2022, as Appl. No. 17/903,894.
Claims priority of application No. 2022-045399 (JP), filed on Mar. 22, 2022.
Prior Publication US 2023/0307537 A1, Sep. 28, 2023
Int. Cl. H01L 29/78 (2006.01); H10D 30/66 (2025.01); H10D 64/00 (2025.01); H10D 64/27 (2025.01)
CPC H10D 30/668 (2025.01) [H10D 64/117 (2025.01); H10D 64/513 (2025.01); H10D 64/516 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first electrode,
a first semiconductor layer of first conductivity type provided on the first electrode;
a second semiconductor layer of first conductivity type provided on the first semiconductor layer;
a first semiconductor region of second conductivity type provided on the second semiconductor layer;
a first insulating film provided in a trench reaching the second semiconductor layer from above the first semiconductor region, a dielectric constant of an upper part of the first insulating film being higher than a dielectric constant of a lower part of the first insulating film;
a second electrode provided in the trench, the second electrode facing the first semiconductor region;
a second insulating film provided between the second electrode and the first semiconductor region, the second insulating film being provided on the first insulating film in the trench;
a second semiconductor region of first conductivity type provided on the first semiconductor region;
an interlayer insulating film provided on the second electrode; and
a third electrode provided on the interlayer insulating film, the third electrode being electrically connected to the second semiconductor region.