CPC H10D 30/668 (2025.01) [H01L 21/26586 (2013.01); H01L 21/266 (2013.01); H10D 30/0297 (2025.01)] | 15 Claims |
1. A method for manufacturing a semiconductor device, comprising:
forming an N-type layer on a first surface of an N+ type substrate,
forming a P type region in the N-type layer,
etching the P type region and the N-type layer to form a trench,
forming a sacrificial layer on an inner bottom surface of the trench,
forming a first mask on an inner side of the trench,
removing the sacrificial layer, and
implanting ions into an inner surface of the trench exposed by the removal of the sacrificial layer to form a P type shield region,
wherein an upper surface of the sacrificial layer is disposed under an interface between the P type region and the N-type layer, and
wherein a height of a channel is adjusted by adjusting a distance between the upper surface of the sacrificial layer and the interface between the P type region and the N-type layer.
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