US 12,342,565 B2
Semiconductor devices and methods of manufacturing thereof
Chia-Cheng Chao, Hsinchu (TW); Hsin-Chieh Huang, Taoyuan (TW); and Yu-Wen Wang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 26, 2022, as Appl. No. 17/584,785.
Claims priority of provisional application 63/211,630, filed on Jun. 17, 2021.
Prior Publication US 2022/0406920 A1, Dec. 22, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/82 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 30/031 (2025.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/30604 (2013.01); H01L 21/308 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
forming a fin structure that comprises a plurality of semiconductor channel layers spaced apart from one another with a plurality of semiconductor sacrificial layers;
forming a semiconductor cladding layer continuously extending along sidewalls of the fin structure; and
patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process, wherein a vertical difference between the highest point and the lowest point is less than 3 nanometers.
 
10. A method for fabricating a semiconductor device, comprising:
forming a first fin structure and a second fin structure parallel with each other, wherein each of the first fin structure and second fin structure comprises a plurality of semiconductor channel layers spaced apart from one another with a plurality of semiconductor sacrificial layers;
forming a semiconductor cladding layer continuously extending along sidewalls of each of the first and second fin structures; and
patterning the semiconductor cladding layer by performing a plurality of sequential combinations of a first etching process and a second etching process, wherein respective first time periods for which the first etching processes of the plurality of sequential combinations are performed are identical to each other, and respective second time periods for which the second etching processes of the plurality of sequential combinations are performed are different from one another.
 
17. A method for fabricating a semiconductor device, comprising:
forming a stack structure including a plurality of silicon (Si) layers and a plurality of germanium (Ge) layers disposed on top of one another, wherein a topmost layer of the stack structure is one of the Si layers;
forming a hard mask over the stack structure, the hard mask containing silicon germanium (SiGe) with a first percentage of Ge;
patterning the stack structure based on the hard mask to form a fin structure;
forming a cladding layer continuously extending along sidewalls of the fin structure, the cladding layer containing SiGe with a second percentage of Ge higher than the first percentage; and
removing the hard mask and patterning the cladding layer by performing at least one sequential combination of a first etching process and a second etching process, thereby causing a vertical difference between a top surface of the topmost layer and a lowest point of a top surface of the cladding layer to be substantially zero.