US 12,342,564 B2
Semiconductor structure and forming method thereof
Hsueh-Han Lu, Tainan (TW); Kun-Ei Chen, Tainan County (TW); Chen-Chieh Chiang, Kaohsiung (TW); and Ling-Sung Wang, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Mar. 17, 2022, as Appl. No. 17/697,575.
Prior Publication US 2023/0299179 A1, Sep. 21, 2023
Int. Cl. H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/024 (2025.01) [H01L 21/0223 (2013.01); H01L 21/0228 (2013.01); H10D 30/6211 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a substrate including a first region and a second region adjacent to the first region;
patterning the substrate to form a first fin structure in the first region and a pair of second fin structures in the second region, wherein the first fin structure is between the pair of second fin structures, and a first width of the first fin structure is greater than a second width of each of the pair of second fin structures;
forming a protecting layer on each of the pair of second fin structures; and
forming a first oxide layer over the first fin structure and forming a second oxide layer over the protecting layer, wherein a width of the first oxide layer is greater than a width of the second oxide layer,
wherein an overall width of the first fin structure and the first oxide layer substantially equals an overall width of one of the pair of second fin structures, the protecting layer and the second oxide layer.