US 12,342,560 B2
Transistors with source-connected field plates
Congyong Zhu, Gilbert, AZ (US); Anthony Ciancio, Gilbert, AZ (US); Fred Reece Clayton, Mesa, AZ (US); Lawrence Scott Klingbeil, Chandler, AZ (US); and Bernhard Grote, Phoenix, AZ (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Dec. 20, 2021, as Appl. No. 17/645,276.
Prior Publication US 2023/0197829 A1, Jun. 22, 2023
Int. Cl. H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01)
CPC H10D 30/015 (2025.01) [H10D 30/471 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01); H10D 64/111 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device comprising:
depositing interlayer dielectric material over a first dielectric layer and a first electrode on a semiconductor substrate, wherein:
the interlayer dielectric material comprises first interlayer dielectric material disposed over the first dielectric layer and a second interlayer dielectric material disposed over the first interlayer dielectric material;
the first dielectric layer is disposed above a channel region of the semiconductor substrate suitable for use as a semiconductive transistor channel;
the first electrode extends within a first aperture in the first dielectric layer and contacts a top surface of the channel region within the aperture; and
the first electrode is disposed between a first current terminal electrically coupled to a first end of the channel region and a second current terminal electrically coupled to a second end the channel region opposite the first end of the channel region;
performing a first patterning step that includes selectively removing the interlayer dielectric material in a first region between the first electrode and the second current terminal, thereby leaving remaining dielectric material that includes the first dielectric layer above the channel region;
forming a second electrode having first and second ends, wherein:
the first end of the second electrode is adjacent to the first electrode in the first region;
the first end of the second electrode is separated from the top surface of the channel region by at least the first dielectric layer;
the second end of the second electrode is disposed above the first electrode and is separated from the first electrode by the remaining interlayer dielectric material; and
forming a conductive interconnect that extends between the first current terminal and the second electrode and electrically couples the second electrode to the first current terminal, the interconnect being disposed above the first electrode and the remaining interlayer dielectric material;
wherein selectively removing the interlayer dielectric material in the first region comprises:
forming a second aperture in the second interlayer dielectric material by removing the second interlayer dielectric material from the first region using a first etching procedure followed by removing the first interlayer dielectric material from the first region using a second etching procedure; and
wherein the first end of the second electrode extends within the second aperture.