US 12,342,557 B2
Semiconductor device and method of manufacturing the same
Yoshito Nakazawa, Tokyo (JP); and Tomohiro Imai, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Aug. 18, 2021, as Appl. No. 17/405,733.
Claims priority of application No. 2020-148585 (JP), filed on Sep. 3, 2020.
Prior Publication US 2022/0102538 A1, Mar. 31, 2022
Int. Cl. H10D 12/00 (2025.01); H10D 12/01 (2025.01)
CPC H10D 12/481 (2025.01) [H10D 12/038 (2025.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a silicon substrate having a first main surface and a second main surface opposite the first main surface;
p-type base layers formed in the first main surface;
an n-type emitter layer formed in one of the p-type base layers;
n-type hole barrier layers formed in the first main surface and formed below the p-type base layers;
a p-type collector layer formed on the second main surface;
an n-type field stop layer formed on the second main surface and formed on an inner side of the p-type collector layer; and
an n-type drift layer arranged between the n-type field stop layer and the n-type hole barrier layers,
wherein the silicon substrate has a first side surface in a plan view,
wherein the n-type field stop layer has a first end portion facing the first side surface of the silicon substrate,
wherein the n-type field stop layer is selectively provided on an upper side of the p-type collector layer such that the first end portion of the n-type field stop layer is separated from the first side surface of the silicon substrate by a predetermined distance,
wherein the n-type drift layer is provided between the first side surface of the silicon substrate and the first end portion of the n-type field stop layer,
wherein the p-type collector layer includes a first p-type collector layer located below the n-type field stop layer and a second p-type collector layer located below the n-type drift layer,
wherein an impurity concentration of the second p-type collector layer is lower than an impurity concentration of the first p-type collector layer, and
wherein a boundary of the first p-type collector layer and the second p-type collector layer is in a chip outer peripheral region outside a cell formation region including the p-type base layers.