US 12,342,550 B2
Memory array structure
Ling Shen, Shanghai (CN); Yu Jiang, Shanghai (CN); Huijie Yan, Shanghai (CN); Zhifang Li, Shanghai (CN); Linmei Dong, Shanghai (CN); Jiebin Duan, Shanghai (CN); and Jianxin Wen, Shanghai (CN)
Assigned to SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO., LTD, Shanghai (CN); and SHANGHAI IC R&D CENTER CO., LTD, Shanghai (CN)
Appl. No. 17/784,652
Filed by SHANGHAI IC R&D CENTER CO., LTD, Shanghai (CN)
PCT Filed Jul. 23, 2020, PCT No. PCT/CN2020/103763
§ 371(c)(1), (2) Date Jun. 12, 2022,
PCT Pub. No. WO2021/135180, PCT Pub. Date Jul. 8, 2021.
Claims priority of application No. 201911388598.5 (CN), filed on Dec. 30, 2019.
Prior Publication US 2023/0005990 A1, Jan. 5, 2023
Int. Cl. H10B 63/00 (2023.01); G06F 7/57 (2006.01); G06N 3/063 (2023.01)
CPC H10B 63/80 (2023.02) [G06F 7/57 (2013.01); G06N 3/063 (2013.01); H10B 63/30 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A memory array structure, comprising an array composed of multiple memory devices arranged in rows and columns, each of the rows is set with a row leading-out wire, and each of the columns is set with a column leading-out wire, the memory devices are correspondingly positioned at intersection points of each the row leading-out wire and each the column leading-out wire; wherein, the first terminal of each of the memory devices is individually connected to the row leading-out wire of the same row, and the second terminal of each of the memory devices is connected to a first terminal of a switch in the same column, the second terminal of the switch is connected to the column leading-out wire of the same column; wherein, each of the columns is set with one to multiple the switches, and the first terminal of each of the switches is connected to one to all of the second terminals of the memory devices in the same column.