US 12,342,548 B2
Memory device and manufacturing method thereof
Chien-Min Lee, Hsinchu County (TW); Cheng-Hsien Wu, Hsinchu (TW); Cheng-Chun Chang, Taoyuan (TW); Elia Ambrosi, Hsinchu (TW); Hengyuan Lee, Hsinchu (TW); Ying-Yu Chen, Yilan (TW); Xinyu Bao, Fremont, CA (US); and Tung-Ying Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 10, 2022, as Appl. No. 17/669,313.
Claims priority of provisional application 63/214,274, filed on Jun. 24, 2021.
Prior Publication US 2022/0415968 A1, Dec. 29, 2022
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/24 (2023.02) [H10B 63/84 (2023.02); H10N 70/026 (2023.02); H10N 70/8828 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
memory cells, each comprising:
a resistance variable storage device; and
an ovonic threshold switch (OTS) selector, stacked with the resistance variable storage device and coupled to the resistance variable storage device with a shared terminal, and comprising a switching layer formed of a chalcogenide compound comprising germanium, carbon, tellurium and nitrogen, wherein nitrogen atoms establish bonding with carbon atoms and germanium atoms in the chalcogenide compound.