US 12,342,543 B2
Three-dimensional nor array and method of making the same
Masaaki Higashitani, Cupertino, CA (US); Peter Rabkin, Cupertino, CA (US); and Hiroyuki Kinoshita, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Jul. 13, 2023, as Appl. No. 18/351,992.
Claims priority of provisional application 63/387,389, filed on Dec. 14, 2022.
Prior Publication US 2024/0206169 A1, Jun. 20, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H10B 43/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a vertical stack of repetition units, wherein each instance of the repetition unit extends along a first horizontal direction and comprises a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip;
source/drain openings arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units; and
source/drain pillar structures located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.