| CPC H10B 43/20 (2023.02) [H10B 43/30 (2023.02); H10B 51/20 (2023.02); H10B 51/30 (2023.02)] | 20 Claims |

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1. A method, comprising:
forming a stack of dummy gate electrode layers arranged between interconnect dielectric layers over a substrate;
forming a first trench within the stack of dummy gate electrode layers;
replacing the stack of dummy gate electrode layers with gate electrode layers;
forming a continuous memory layer, a continuous channel layer, and a continuous dielectric layer within the first trench;
filling remaining portions of the first trench with a fourth dielectric material;
forming fourth openings within the fourth dielectric material to form first barrier structures within the first trench;
forming a continuous protective liner layer within the fourth openings;
forming sacrificial structures within the fourth openings;
removing portions of the continuous protective liner layer and portions of the sacrificial structures to respectively form a first protective liner layer and fifth openings within the sacrificial structures, and leaving remaining portions of the sacrificial structures in place;
forming a second protective liner layer within the fifth openings of the sacrificial structures;
forming second barrier structures within remaining portions of the fifth openings; and
removing the remaining portions of the sacrificial structures and replacing the remaining portions of the sacrificial structures with a conductive material to form source/drain conductive lines surrounded by the first protective liner layer and the second protective liner layer.
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