US 12,342,528 B2
Semiconductor device and manufacturing method
Seongjin Jeong, Seoul (KR); Seokhan Park, Seongnam-si (KR); Yejee Sunwoo, Seoul (KR); Bowon Yoo, Suwon-si (KR); and Youngwoong Son, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 25, 2022, as Appl. No. 17/872,143.
Claims priority of application No. 10-2021-0104899 (KR), filed on Aug. 9, 2021.
Prior Publication US 2023/0039823 A1, Feb. 9, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/033 (2023.02); H10B 12/09 (2023.02); H10B 12/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate including a cell area and a peripheral circuit area, wherein the cell area includes cell transistors and the peripheral circuit area includes a peripheral circuit;
an etching stop layer including a first portion of the etching stop layer arranged in the cell area and a second portion of the etching stop layer arranged in the peripheral circuit area; and
a capacitor structure arranged in the cell area and including lower electrodes respectively connected to the cell transistors via the first portion of the etching stop layer and arranged according to a first pitch,
wherein the second portion of the etching stop layer includes recesses arranged according to a second pitch substantially the same as the first pitch,
wherein the etching stop layer comprises a first thickness at each recess and a second thickness between adjacent recesses, and
wherein the second thickness is greater than the first thickness.