| CPC H10B 10/125 (2023.02) [G11C 11/412 (2013.01); H10B 10/00 (2023.02); H10B 10/12 (2023.02)] | 20 Claims |
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1. A static random-access memory (SRAM) device including a three-dimensional structured (3DS) field-effect transistor (FET), the SRAM device comprising:
a semiconductor substrate;
a first fin active region extending on the semiconductor substrate in a first direction and including a first region and a second region, wherein in the first region and the second region, a first lower layer is arranged, wherein only in the second region, a first upper layer is arranged on the first lower layer, and wherein the second region is to the right of the first region;
a second fin active region extending on the semiconductor substrate in the first direction and including a third region and a fourth region, wherein in the third region and the fourth region, a second lower layer is arranged, wherein only in the fourth region, a second upper layer is arranged on the second lower layer, wherein the fourth region is to the left of the third region, and wherein the second fin active region is spaced apart from the first fin active region in a second direction perpendicular to the first direction;
a first gate electrode extending along a first straight line extending in the second direction and intersecting the first region;
a second gate electrode extending along a second straight line extending in the second direction and intersecting the second region, wherein the first gate electrode and the second gate electrode are spaced apart from each other in the first direction;
a third gate electrode extending along the second straight line extending in the second direction and being separate from the second gate electrode in the second direction, and intersecting the third region;
a fourth gate electrode extending along the first straight line extending in the second direction and being separate from the first gate electrode in the second direction, and intersecting the fourth region, wherein the third gate electrode and the fourth gate electrode are spaced apart from each other in the first direction;
a first node connecting the fourth gate electrode to the second region of the first fin active region; and
a second node connecting the second gate electrode to the fourth region of the second fin active region,
wherein the first node includes a first portion connected to the fourth gate electrode and a second portion connected to the second region of the first fin active region,
wherein the second portion of the first node is buried in the first lower layer of the first fin active region and contacts a side surface of the first upper layer of the second region of the first fin active region,
wherein the first gate electrode and the first lower layer of the first region constitute a first pass transistor,
wherein the second gate electrode and the first lower layer of the second region constitute a first pull-down transistor,
wherein the second gate electrode and the first upper layer of the second region constitute a first pull-up transistor,
wherein the third gate electrode and the second lower layer of the third region constitute a second pass transistor,
wherein the fourth gate electrode and the second lower layer of the fourth region constitute a second pull-down transistor, and
wherein the fourth gate electrode and the second upper layer of the fourth region constitute a second pull-up transistor.
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