| CPC H10B 10/12 (2023.02) [G11C 11/412 (2013.01); G11C 11/419 (2013.01); H10B 10/18 (2023.02)] | 6 Claims |
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1. A semiconductor storage device including a one-port SRAM cell, the one-port SRAM cell comprising:
a first transistor connected to a first power supply supplying a first voltage at one of its nodes, to a first node at the other node, and to a second node at its gate;
a second transistor connected to the first power supply at one of its nodes, to the second node at the other node, and to the first node at its gate;
a third transistor connected to the first node at one of its nodes, to a second power supply supplying a second voltage different from the first voltage at the other node, and to the second node at its gate;
a fourth transistor connected to the second node at one of its nodes, to the second power supply at the other node, and to the first node at its gate;
a fifth transistor connected to a first bit line at one of its nodes, to the first node at the other node, and to a word line at its gate; and
a sixth transistor connected to a second bit line at one of its nodes, to the second node at the other node, and to the word line at its gate, the first bit line and the second bit line constituting a complementary bit line pair,
wherein
the first to sixth transistors respectively include
first to sixth nanosheets extending in a first direction, and
first to sixth gate interconnects surrounding the first to sixth nanosheets, respectively, in a second direction vertical to the first direction and in a third direction perpendicular to the first and second directions,
the sixth, first, and third nanosheets are formed in line in this order in the second direction,
the fourth, second, and fifth nanosheets are formed in line in this order in the second direction,
faces of the fourth and sixth nanosheets on a first side that is close to a cell boundary in the second direction are exposed from the fourth and sixth gate interconnects,
faces of the third and fifth nanosheets on a second side that is opposite to the first side in the second direction are exposed from the third and fifth gate interconnects,
a face of the second nanosheet on the second side is exposed from the second gate interconnect, and
a face of the first nanosheet on the first side is exposed from the first gate interconnect.
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