US 12,342,034 B2
Multi-display video synchronization
Karthik Tyamgondlu, Chandler, AZ (US); Benjamin Thomas Cope, Loudwater (GB); Satyeshwar Singh, Folsom, CA (US); Sangeeta Ghangam Manepalli, Chandler, AZ (US); and Aswin Padmanabhan, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,497.
Prior Publication US 2022/0116678 A1, Apr. 14, 2022
Int. Cl. H04N 5/45 (2011.01); G09G 3/36 (2006.01); H03L 7/08 (2006.01); H04N 21/43 (2011.01)
CPC H04N 21/43076 (2020.08) [H03L 7/08 (2013.01); H04N 21/4305 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A system, comprising:
a processor;
a display controller;
a display interface to connect the display controller to a display; and
a network interface to connect the system to a network;
wherein the processor is to execute instructions that cause the processor to:
cause a request to be transmitted over the network to a primary system to obtain a first set of VSYNC timestamps for the primary system;
access the first set of VSYNC timestamps received based on the request;
access a second set of VSYNC timestamps based on interrupts generated by the display controller;
determine an adjustment factor based on a comparison of the first and second VSYNC timestamps;
program an adjusted VSYNC period for the display controller based on the determined adjustment factor; and
revert back to an original VSYNC period for the display controller after a predetermined number of VSYNC cycles.