US 12,341,709 B2
Configurable receive buffer size
Noam Elati, Zichron Yaakov (IL); Boris Kleiman, Rishon LeZion (IL); and Piotr Uminski, Gdynia (PL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 26, 2021, as Appl. No. 17/359,542.
Prior Publication US 2021/0328945 A1, Oct. 21, 2021
Int. Cl. H04L 47/52 (2022.01); H04L 49/9005 (2022.01); H04L 49/901 (2022.01); H04L 49/9047 (2022.01)
CPC H04L 49/9005 (2013.01) [H04L 49/901 (2013.01); H04L 49/9047 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a network interface device comprising:
a host interface;
a network interface;
a direct memory access (DMA) circuitry; and
circuitry to:
allocate a first number of buffers to store received packets associated with a first descriptor ring;
allocate a second number of buffers to store received packets associated with a second descriptor ring; and
based on receipt of a packet, copy the received packet into a number of buffers based on whether the received packet is associated with the first descriptor ring or the second descriptor ring, wherein the number of buffers allocated to store the received packet is based on a number of descriptors associated with the received packet and the number of buffers allocated to store the received packet is greater than one.