US 12,341,532 B2
Accelerated polynomial coding system and method
Michael H. Anderson, Udon Thani (TH)
Assigned to STREAMSCALE, INC., Waco, TX (US)
Filed by DARK MATTER COMPUTING, INC., Waco, TX (US)
Filed on Nov. 1, 2023, as Appl. No. 18/386,183.
Application 18/386,183 is a continuation of application No. 17/747,828, filed on May 18, 2022, granted, now 11,848,686.
Prior Publication US 2024/0063825 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/11 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 15/80 (2006.01); H03M 13/00 (2006.01); H03M 13/03 (2006.01); H03M 13/15 (2006.01); H04L 1/00 (2006.01); H04L 1/1812 (2023.01)
CPC H03M 13/1575 (2013.01) [G06F 9/4881 (2013.01); G06F 9/5027 (2013.01); G06F 15/8007 (2013.01); H03M 13/154 (2013.01); H03M 13/6516 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system adapted to use accelerated error-correcting code (ECC) processing to improve the storage and retrieval of digital data distributed across a plurality of drives, comprising:
at least one processor comprising at least one single-instruction-multiple-data (SIMD) processing core that executes SIMD instructions loaded from at least one non-volatile storage medium and loads original data from a memory and stores check data to the memory, the SIMD processing core comprising a plurality of vector registers, each of the vector registers storing at least 16 bytes;
a plurality of data drives each comprising at least one non-volatile storage medium that stores at least one block of the original data, the at least one block comprising at least 512 bytes;
more than two check drives each comprising at least one non-volatile storage medium that stores at least one block of the check data; and
at least one input/output (I/O) controller that stores the at least one block of the check data from the memory to the check drives,
wherein the processor, the SIMD instructions, the at least one non-volatile storage medium, and the I/O controller implement a polynomial coding system comprising:
a data matrix comprising at least one vector and comprising a plurality of rows of at least one block of the original data in the memory, each of the rows being stored on a different one of the data drives;
a check matrix comprising more than two rows of the at least one block of the check data in the memory, each of the rows being stored on a different one of the check drives; and
a thread that executes on the SIMD processing core and comprising:
at least one parallel multiplier that multiplies the at least one vector of the data matrix by a single factor to compute parallel multiplier results comprising at least one vector; and
a parallel linear feedback shift register (LFSR) sequencer wherein the parallel LFSR sequencer orders load operations of the original data into at least one of the vector registers and computes the check data with the at least one parallel multiplier and stores the computed check data from the vector registers to the memory.