US 12,341,524 B2
Clock generation circuit, and semiconductor device and semiconductor system using the clock generation circuit
Young Jae An, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Sep. 29, 2023, as Appl. No. 18/478,667.
Claims priority of application No. 10-2023-0069037 (KR), filed on May 30, 2023.
Prior Publication US 2024/0405777 A1, Dec. 5, 2024
Int. Cl. H03L 7/081 (2006.01); H03K 5/156 (2006.01); H03L 7/085 (2006.01); H04L 7/00 (2006.01)
CPC H03L 7/0816 (2013.01) [H03K 5/1565 (2013.01); H03L 7/085 (2013.01); H04L 7/0037 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A clock generation circuit comprising:
a delay-locked circuit configured to generate a delay clock signal by delaying an input clock signal and configured to update a delay time of the input clock signal by comparing phases of the input clock signal and a feedback clock signal; and
a duty correction circuit configured to generate a first phase clock signal and a second phase clock signal by delaying the delay clock signal, configured to update a delay time of the delay clock signal by comparing phases of the first and second phase clock signals, and configured to prevent the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.