US 12,341,520 B2
Glitch reduction in high-speed differential receivers
Jitender Kapil, Bangalore (IN); and Srikanth Vellore Avadhanam Ramamurthy, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on May 31, 2023, as Appl. No. 18/326,418.
Prior Publication US 2024/0405760 A1, Dec. 5, 2024
Int. Cl. H03K 5/1252 (2006.01); H03K 5/24 (2006.01)
CPC H03K 5/1252 (2013.01) [H03K 5/2481 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A receiver circuit, comprising:
an attenuator circuit having first and second inputs and first and second outputs, the attenuator circuit including a resistor network coupled to the first and second inputs and to the first and second outputs;
a comparator having first and second inputs and an output;
a buffer having an input coupled to the output of the comparator, and having an output;
a first switch having a first terminal coupled to the first output of the attenuator circuit and a second terminal coupled to the first input of the comparator;
a second switch having a first terminal coupled to the second output of the attenuator circuit and a second terminal coupled to the second input of the comparator; and
a first current source coupled to the first input of the comparator;
a second current source coupled to the second input of the comparator; and
third and fourth switches coupled in series between the first and second current sources.