US 12,341,514 B1
Controlling and powering multiple chips
Shahriar Ilislamoo, San Jose, CA (US); David Carlson, Haslet, TX (US); Barun Kar, Saratoga, CA (US); and Darshan Shah, Milpitas, CA (US)
Assigned to Auradine, Inc., Santa Clara, CA (US)
Filed by Auradine, Inc., Santa Clara, CA (US)
Filed on Jan. 23, 2025, as Appl. No. 19/035,308.
Claims priority of provisional application 63/568,375, filed on Mar. 21, 2024.
Int. Cl. H03K 19/23 (2006.01); G06F 7/57 (2006.01); H03K 19/08 (2006.01)
CPC H03K 19/23 (2013.01) [G06F 7/57 (2013.01); H03K 19/08 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An electronic circuit, comprising:
an event detector logic circuit;
a computing device; and
a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit,
wherein the event detector logic circuit is configured to:
receive a plurality of output signals from the plurality of IC chips,
generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, the data output signal generated such that the data is included in the data output signal independently of a presence and polarity of any static output signals of the plurality of output signals, and
transmit the data output signal to the computing device.