|
1. A logic gate comprising at least two phase change memory—PCM—cells, said at least two PCM cells having a high resistance phase and a low resistance phase, said at least two PCM cells being connected at a common connection and further the logic gate having at least one gate input for an input logic state, wherein a logic output for the logic gate comprises a phase of an output one of said at least two phase change memory cells, the phase of the output one of said at least two phase change memory cells forming the logic output following provision of said input logic state at said gate input, the logic gate being configured to react to a set pulse and a reset pulse as logic input pulses, wherein the set pulse is configured to raise a temperature of the cell to a crystallization temperature and the reset pulse is configured to raise the temperature of the cell to a melting temperature, wherein the at least two PCM cells comprise three PCM cells, said three PCM cells being connected between respective inputs and said common connection, said common connection being connected to a resistance.
|
