US 12,341,502 B2
Driver circuitry and electronic circuitry
Ryo Isoe, Kawasaki Kanagawa (JP); and Yuichi Goto, Hiratsuka Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Sep. 13, 2023, as Appl. No. 18/367,761.
Claims priority of application No. 2023-014903 (JP), filed on Feb. 2, 2023.
Prior Publication US 2024/0267046 A1, Aug. 8, 2024
Int. Cl. H03K 17/16 (2006.01); H03K 17/687 (2006.01); H03K 19/003 (2006.01); H03K 19/0948 (2006.01)
CPC H03K 17/161 (2013.01) [H03K 17/687 (2013.01); H03K 19/00315 (2013.01); H03K 19/00361 (2013.01); H03K 19/0948 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A driver circuitry that is a circuitry for driving a high withstand voltage element having withstand voltage performance against a first withstand voltage, the driver circuitry comprising:
a first transistor in which a first voltage is applied to a first end thereof, and a second end thereof is connected to a drive terminal of the high withstand voltage element, and which is a p-channel Metal-Oxide-Semiconductor Field-Effect Transistor (pMOS) having withstand voltage performance against the first withstand voltage;
a second transistor in which a first end thereof is connected to the second end of the first transistor, and a second voltage is applied to a second end thereof, and which is an n-channel MOSFET (nMOS) having withstand voltage performance against the first withstand voltage;
a first inverter to which a drive signal is input from a first end thereof, and which is formed of an element having withstand voltage performance against a second withstand voltage lower than the first withstand voltage;
a second inverter in which a first end thereof is connected to the second end of the first inverter, and a second end thereof is connected to a drive terminal of the first transistor, and which is formed of an element having withstand voltage performance against the second withstand voltage;
a third inverter in which a first end thereof is connected to the first end of the first inverter, and which is formed of an element having withstand voltage performance against the second withstand voltage;
a third transistor in which a first end thereof is connected to the second end of the second inverter, and which is a pMOS having withstand voltage performance against the first withstand voltage;
a fourth transistor in which a first end thereof is connected to a second end of the third transistor, and which is an nMOS having withstand voltage performance against the first withstand voltage;
a fifth transistor in which a first end thereof is connected to a second end of the third inverter, and which is a pMOS having withstand voltage performance against the first withstand voltage;
a sixth transistor in which a first end thereof is connected to a second end of the fifth transistor, and which is an nMOS having withstand voltage performance against the first withstand voltage;
a fourth inverter in which a first end thereof is connected to a second end of the sixth transistor, and a second end thereof is connected to a drive terminal of the second transistor, and which is formed of an element having withstand voltage performance against the second withstand voltage; and
a fifth inverter in which a first end thereof is connected to a second end of the fourth transistor and the second end of the fourth inverter, and a second end thereof is connected to the first end of the fourth inverter, and which is formed of an element having withstand voltage performance against the second withstand voltage.