US 12,341,501 B2
Accurate reduced gate-drive current limiter
Satish Kumar Vangara, Woodley (GB); Antony Christopher Routledge, Basingstoke Hampshire (GB); Gregory Szczeszynski, Nashua, NH (US); and Xiaowu Sun, Milford, NH (US)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Kyoto (JP)
Filed on Feb. 7, 2024, as Appl. No. 18/435,509.
Application 18/435,509 is a continuation of application No. 17/959,904, filed on Oct. 4, 2022, granted, now 11,936,371.
Prior Publication US 2024/0259014 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 17/08 (2006.01); H03K 5/08 (2006.01); H03K 17/082 (2006.01)
CPC H03K 17/0822 (2013.01) [H03K 5/086 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A gate control circuit for regulating the ON resistance, RON, of a power FET, including:
a source-follower circuit including a source-follower FET having a conduction channel configured to be coupled to a gate of the power FET and configured to selectively apply at least a first voltage or a second voltage to the gate of the power FET such that the RON of the power FET in an ON state is lower when the first voltage is applied and higher when the second voltage is applied; and
a compensation circuit coupled to one of a gate of the source-follower FET or an output of the source-follower FET and configured to apply a compensation voltage boost to adjust the second voltage to the gate of the power FET to compensate for a gate capacitance of the power FET.