US 12,341,474 B2
Transistor bias adjustment for optimization of third order intercept point in a cascode amplifier
Rong Jiang, San Diego, CA (US); and Haopei Deng, San Diego, CA (US)
Assigned to pSemi Corporation
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Jan. 30, 2024, as Appl. No. 18/427,472.
Application 18/427,472 is a continuation of application No. 17/737,878, filed on May 5, 2022, granted, now 11,894,809.
Application 17/737,878 is a continuation of application No. 16/294,637, filed on Mar. 6, 2019, granted, now 11,329,611, issued on May 10, 2022.
Prior Publication US 2024/0283407 A1, Aug. 22, 2024
Int. Cl. H03F 1/02 (2006.01); H03F 1/22 (2006.01); H03F 1/32 (2006.01); H03F 1/56 (2006.01); H03F 3/02 (2006.01); H03F 3/195 (2006.01); H03F 3/21 (2006.01); H03G 3/30 (2006.01)
CPC H03F 1/223 (2013.01) [H03F 1/3205 (2013.01); H03F 1/565 (2013.01); H03F 3/02 (2013.01); H03F 3/195 (2013.01); H03F 3/21 (2013.01); H03G 3/3042 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method for reducing non-linearities in a multi-gain-state cascode amplifier, the method comprising:
during operation in a low gain-state, establishing a low gain by providing a first biasing voltage to a gate of an input transistor of the cascode amplifier;
during operation in a high gain-state, establishing a high gain by providing a second biasing voltage to the gate of the input transistor; and
reducing non-linearities during operation in the low gain-state and high gain-state by tuning a biasing voltage to a gate of a cascode transistor of the cascode amplifier,
wherein tuning of the biasing voltage includes
increasing a drain-to-source voltage of the input transistor in the low gain-state, and
increasing a drain-to-source voltage of the cascode transistor in the high gain-state, and
wherein the providing and the tuning of the biasing voltages comprises selective generation of the biasing voltages based on decoding of an input control signal into a target gain-state that comprises the low gain-state or the high gain-state.