US 12,341,434 B2
Power supply with active power buffer
Yantao Song, Northville, MI (US); Chanwit Prasantanakorn, Santa Clara, CA (US); Bharat K Patel, San Martin, CA (US); and Abby Cherian, Fremont, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 12, 2022, as Appl. No. 17/663,143.
Claims priority of provisional application 63/268,665, filed on Feb. 28, 2022.
Prior Publication US 2023/0275521 A1, Aug. 31, 2023
Int. Cl. H02M 1/42 (2007.01); H02M 1/00 (2006.01); H02M 3/335 (2006.01); H02M 7/217 (2006.01)
CPC H02M 3/33592 (2013.01) [H02M 1/007 (2021.05); H02M 1/4208 (2013.01); H02M 1/4258 (2013.01); H02M 7/217 (2013.01); H02M 1/4225 (2013.01); H02M 3/33507 (2013.01); H02M 3/33523 (2013.01); H02M 3/33569 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A power converter comprising:
a rectifier that receives an AC input voltage and produces a rectified output voltage;
a power factor correction (PFC) converter having an input coupled that receives the rectified output voltage of the rectifier and an output that provides an intermediate DC bus voltage;
a DC-DC converter having an input that receives the intermediate DC bus voltage and produces a regulated DC output voltage; and
control circuitry for the PFC converter that includes a relatively slower control loop that controls the PFC converter during steady state load conditions and at least one relatively faster control loop that controls the PFC converter during transient load conditions, wherein the at least one relatively faster control loop compares the intermediate DC bus voltage to a reference voltage that is different than a reference voltage of the relatively slower control loop;
wherein the at least one relatively faster control loop comprises a first relatively faster control loop that controls the PFC converter during transient load conditions resulting from a load increase and a second relatively faster control loop that controls the PFC converter during transient load condition resulting from a load decrease, and
wherein the control circuitry further comprises selection circuitry that selects a reference signal from among output signals of the relatively slower control loop, the first relatively faster control loop, and the second relatively faster control loop.