US 12,341,415 B2
Low noise gate driver circuits
Syed Wasif Mehdi, Freising (DE); and Stefan Herzer, Marzling (DE)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 27, 2022, as Appl. No. 18/050,220.
Prior Publication US 2024/0146177 A1, May 2, 2024
Int. Cl. H02M 1/08 (2006.01); H02M 1/00 (2006.01); H02M 1/44 (2007.01)
CPC H02M 1/08 (2013.01) [H02M 1/0054 (2021.05); H02M 1/44 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A gate driver circuit, comprising:
a charge pump circuit having a charge pump output;
a first transistor having a first current terminal, a second current terminal, and a first control terminal, in which the first current terminal is coupled to the charge pump output;
a first resistor coupled between a power input terminal and the first control terminal; and
a first capacitor coupled between the first control terminal and a ground terminal, wherein the charge pump circuit includes a second capacitor having a top plate coupled to the first current terminal, and a bottom plate, a first inverter circuit including an inverter input and an inverter output coupled to the bottom plate, and a second transistor having a third current terminal coupled to the power input terminal, a fourth current terminal coupled to the inverter input, and a second control terminal coupled to the top plate.