US 12,341,134 B2
Microelectronic devices, and methods of forming microelectronic devices
Fatma Arzum Simsek-Ege, Boise, ID (US); and Yuan He, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 29, 2023, as Appl. No. 18/478,821.
Application 18/478,821 is a division of application No. 17/344,444, filed on Jun. 10, 2021, granted, now 11,810,901.
Prior Publication US 2024/0038730 A1, Feb. 1, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); H10B 12/00 (2023.01); H10D 87/00 (2025.01)
CPC H01L 25/0657 (2013.01) [H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 24/32 (2013.01); H01L 2224/32145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H10B 12/50 (2023.02); H10D 87/00 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A microelectronic device, comprising:
a memory array region comprising vertical stacks of memory cells;
conductive lines laterally extending through the vertical stacks of memory cells, each conductive line of the conductive lines associated with a level of the memory cells of the vertical stacks of memory cells;
conductive pillars vertically extending through the vertical stacks of memory cells, each conductive pillar of the conductive pillars vertically extending through access devices of the vertical stacks of memory cells;
a first complementary metal oxide semiconductor region vertically underlying the memory array region and comprising control logic devices for effectuating at least a portion of control operations for the vertical stacks of memory cells; and
a second complementary metal oxide semiconductor region vertically overlying the memory array region, the second complementary metal oxide semiconductor region comprising different control logic devices than the first complementary metal oxide semiconductor region.