US 12,341,110 B2
Methods and apparatus for using structural elements to improve drop/shock resilience in semiconductor devices
Koustav Sinha, Boise, ID (US); Quang Nguyen, Boise, ID (US); Christopher Glancey, Boise, ID (US); and Shams U. Arifeen, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 2, 2022, as Appl. No. 17/591,519.
Claims priority of provisional application 63/238,051, filed on Aug. 27, 2021.
Prior Publication US 2023/0061955 A1, Mar. 2, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 23/49838 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor package assembly, comprising:
a first mounting surface of a package substrate facing a second mounting surface of a printed circuit board;
a first structural element bond pad mounted to the first mounting surface;
a second structural element bond pad mounted to the second mounting surface, the first and second structural element bond pads aligned with each other; and
a structural element interconnected with a first solder joint to the first structural element bond pad and interconnected with a second solder joint to the second structural element bond pad; and
an additional structural element interconnected with a third solder joint to the first structural element bond pad and interconnected with a fourth solder joint to the second structural element bond pad, wherein the structural element and the additional structural element extend between the first and second structural element bond pads to absorb mechanical shock when a compressive force pushes one of the first and second mounting surfaces toward the other.