US 12,341,107 B2
Semiconductor device and method of manufacturing thereof
Yi Seul Han, Incheon (KR); Tae Yong Lee, Goyang-si (KR); and Ji Yeon Ryu, Incheon (KR)
Assigned to Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed on Jul. 12, 2021, as Appl. No. 17/372,850.
Application 17/372,850 is a continuation of application No. 16/564,321, filed on Sep. 9, 2019, granted, now 11,063,001.
Application 16/564,321 is a continuation of application No. 16/053,310, filed on Aug. 2, 2018, granted, now 10,410,973, issued on Sep. 10, 2019.
Application 16/053,310 is a continuation of application No. 15/469,008, filed on Mar. 24, 2017, granted, now 10,177,095, issued on Jan. 8, 2019.
Prior Publication US 2022/0077074 A1, Mar. 10, 2022
Int. Cl. H01L 23/552 (2006.01); H01L 21/50 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/16 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 21/56 (2013.01); H01L 23/16 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 24/13 (2013.01); H01L 24/96 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/49816 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/18 (2013.01); H01L 2224/96 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/3025 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing an electronic device, the method comprising:
providing a first structure comprising:
a signal distribution structure (SDS) comprising a top SDS side, a bottom SDS side, a lateral SDS side, and an SDS conductive layer;
a first electronic component coupled to the top SDS side and comprising a first interconnect coupled to the SDS conductive layer;
a second electronic component coupled to the top SDS side and comprising a second interconnect coupled to the SDS conductive layer;
a conductive shielding member (CSM) coupled to the top SDS side and positioned directly between the first and second electronic components, where the conductive shielding member (CSM) comprises:
a bottom CSM side that is coupled to the top SDS side;
a top CSM side; and
a lateral CSM side; and
an encapsulating material that covers at least a portion of the top SDS side, at least a portion of a lateral side of the first electronic component, at least a portion of a lateral side of the second electronic component, and at least a portion of a lateral side of the conductive shielding member (CSM); and
after said providing the first structure:
forming an electromagnetic interference (EMI) shield layer on a top side of the encapsulating material and on the top CSM side, where the EMI shield layer comprises a bottom side that is coupled to the top CSM side,
wherein said providing the first structure comprises connecting the bottom CSM side and the top SDS side with a solderless connection.