US 12,341,103 B2
Integrated circuit and method of manufacturing same
Pochun Wang, Hsinchu (TW); Ting-Wei Chiang, Hsinchu (TW); Chih-Ming Lai, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Jung-Chan Yang, Hsinchu (TW); Ru-Gun Liu, Hsinchu (TW); Ya-Chi Chou, Hsinchu (TW); Yi-Hsiung Lin, Hsinchu (TW); Yu-Xuan Huang, Hsinchu (TW); Yu-Jung Chang, Hsinchu (TW); Guo-Huei Wu, Hsinchu (TW); and Shih-Ming Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 7, 2022, as Appl. No. 18/053,012.
Application 16/936,249 is a division of application No. 16/135,684, filed on Sep. 19, 2018, granted, now 10,734,321, issued on Aug. 4, 2020.
Application 18/053,012 is a continuation of application No. 16/936,249, filed on Jul. 22, 2020, granted, now 11,508,661.
Claims priority of provisional application 62/564,663, filed on Sep. 28, 2017.
Prior Publication US 2023/0060387 A1, Mar. 2, 2023
Int. Cl. H01L 23/48 (2006.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01)
CPC H01L 23/535 (2013.01) [G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 21/76895 (2013.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first active region and a second active region in a substrate, the first active region and the second active region extending in a first direction, being located on a first level, and being separated from one another in a second direction different from the first direction;
a first conductive structure extending in the first direction, being located on the first level, and being between the first active region and the second active region;
an insulating region located on at least the first level, and being between the first active region, the second active region and the first conductive structure;
a set of gates extending in the second direction, overlapping at least the first conductive structure, and being located on a second level different from the first level, each gate of the set of gates being separated from an adjacent gate of the set of gates in the first direction by a first pitch;
a set of contacts extending in the second direction, overlapping the first conductive structure, and being located on the second level, each contact of the set of contacts being separated from an adjacent contact of the set of contacts in the first direction, and a first contact of the set of contacts being directly coupled to a first source/drain of the first active region; and
a first set of vias coupling the first conductive structure to the set of contacts, the first set of vias being between the first conductive structure and the set of contacts, and a first via of the first set of vias being located where the first contact of the set of contacts overlaps the first conductive structure.