US 12,341,085 B2
Stacked integrated circuit devices
Jung Ho Do, Hwaseong-si (KR); and Seungyoung Lee, Albany, NY (US)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 25, 2024, as Appl. No. 18/646,015.
Application 18/646,015 is a continuation of application No. 18/327,291, filed on Jun. 1, 2023, granted, now 12,002,738.
Application 18/327,291 is a continuation of application No. 17/540,303, filed on Dec. 2, 2021, granted, now 11,699,636, issued on Jul. 11, 2023.
Application 17/540,303 is a continuation of application No. 16/947,241, filed on Jul. 24, 2020, granted, now 11,222,831, issued on Jan. 11, 2022.
Claims priority of provisional application 63/034,525, filed on Jun. 4, 2020.
Prior Publication US 2024/0274510 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H10D 84/83 (2025.01); H10D 89/10 (2025.01)
CPC H01L 23/481 (2013.01) [H10D 84/83 (2025.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a substrate;
an upper transistor;
a lower transistor that is between, in a vertical direction, the substrate and the upper transistor; and
a power via that is adjacent and overlaps, in a horizontal direction, a sidewall of the lower transistor and a sidewall of the upper transistor.