US 12,341,057 B2
Interconnect line for semiconductor device
Chung-Wen Wu, Zhubei (TW); Chih-Yuan Ting, Taipei (TW); and Jyu-Horng Shieh, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2022, as Appl. No. 17/869,177.
Application 16/568,453 is a division of application No. 15/489,511, filed on Apr. 17, 2017, granted, now 10,522,391, issued on Dec. 31, 2019.
Application 15/489,511 is a division of application No. 13/891,578, filed on May 10, 2013, granted, now 9,627,250, issued on Apr. 18, 2017.
Application 17/869,177 is a continuation of application No. 16/568,453, filed on Sep. 12, 2019, granted, now 11,398,405.
Claims priority of provisional application 61/777,219, filed on Mar. 12, 2013.
Prior Publication US 2022/0359274 A1, Nov. 10, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/762 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H10K 71/20 (2023.01)
CPC H01L 21/76802 (2013.01) [H01L 21/762 (2013.01); H01L 21/76804 (2013.01); H01L 21/76805 (2013.01); H01L 21/76829 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H10K 71/231 (2023.02); H01L 21/76885 (2013.01); H01L 2924/0002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first dielectric layer;
a first metal feature in the first dielectric layer, the first metal feature extending above an upper surface of the first dielectric layer;
an etching stop layer (ESL) over the first dielectric layer and the first metal feature, the ESL comprising a single layer;
a second dielectric layer above the ESL; and
a conductive feature extending through the second dielectric layer and into the single layer, the conductive feature contacting a top surface of the first metal feature, wherein the conductive feature protrudes through the single layer, a first sidewall of the first metal feature being between a first sidewall of the conductive feature in the single layer and a second sidewall of the first metal feature, and the second sidewall of the first metal feature being between a second sidewall of the conductive feature in the single layer and the first sidewall of the first metal feature, wherein the top surface of the first metal feature is lower than a top surface of the single layer, wherein the top surface of the first metal feature is higher than a bottom surface of the single layer.